That’s a very tricky question because any assumption I would make is inherently wrong, but I can dream though. I think that the current way of chip design, which AMD pioneered a few years ago with their Zen architecture and now the Zen 2 architecture, is that they split up their logic and their compute into two different dyes. Up until a few years ago, every chip was made as a monolithic block of silicon, which made it prone to an error, which you could bin the CPU if it has a flaw.
So it would render it utterly useless, which makes it very expensive. So you can only get X amount of CPUs out of a big circular die, which they make the chips out of. But if you make the… compute parts very small, like on the new process, the seven nanometers, then you can have a lot of seven nanometer parts.
And if you have a very good yield, that means that the defect density on these 300 millimeters of wafer that they use is very small. That means that the chance that such one of these small chips… is defective and can’t be sold or is a lower tier part, it’s very low. So that’s very lucrative.
On the other hand, it’s less expensive to do your logic part or the part that does the interaction with your different buses to your cards and the memory and your USB, et cetera. If you make it on the current process, which is refined and cheap, and has very good yields, then you can make those two on a separate assembly line and merge them together at the last part. So I think that is a part of technology that Intel is also going to pursue because they also announced it.
They’re going to call it Voveros. But they’re doing it slightly different. They’re going to stack the different layers of the silicon on top of each other.
So they’re planning to do the I.O. part and then the compute part on top of that and then maybe a stack or two of memory on it. So system on a chip is going to become a whole different meaning. So I think that is going to be the future going ahead, stacking everything on top of each other because the time it needs the single to run from A to B is also going to be important.
Less latency is more performance. And just makes up for very cool chips. And just from a physics point of view, how do you cool a stack of very hot running silicon that’s stacked on top of each other?
How do you do that? So… Except that, we’re just going to go down the nanometer rabbit hole any further, even further.
We’re currently at the, quotes, seven nanometer process. We’re going to go to, I think, six. step between that uh five three uh one and a half and then beyond that it’s it’s it’s uh not certain um we have the new machines um that that are being built um that are going to make it possible, that run ultraviolet light as a very, very, very short wavelength in order to make those patterns on the wafers happen, which use up a few kilowatts, if not more, of power just in order to run that laser beam in order to make… the ultraviolet light happen. It’s going to be some crazy physics involved, which is a different and interesting part of it.
But those two things, just scaling it down, down, down, down, down, and trying to stack things up on top of each other or just using different chiplets, as they say, in order to combine awesome things, which also makes it possible to have a chiplet for purely graphics and then for graphics uh level 4 cache or just your memory and your i o and your compute so you can just make a chip a la carte if you want to make a super computer for example which you which you can just make whatever you want tailor-purposed so that’s cool so cpus are going to become more modular Yeah, pretty much modular because it’s just no longer doable to make monolithic mega dies because if you shrink down your transistors even further and further and further and further, if there is a defect happening, the defect will cover more and more transistors, which… Those chips are built for somewhat redundancy. If a cluster of transistors is hit, there’s somewhat of a backup routing path or something else, or parts of the chips they can turn off in order to sell it as a lower tier part.
But that’s going to be an issue. And that’s why they’re probably also from an economic standpoint are going to do that. But I do remember that I said those nanometers, that they weren’t all that.
It’s more of a marketing term somewhat earlier in the podcast. And before I forget to explain that, I’ll just jump into that. The term nanometers was used up until a year or eight ago, I think, for the actual feature size of a transistor.
So gate pitch, et cetera. But don’t go in that because that’s a whole other podcast on its own if it needs to be. But that was the actual physical manifestation of a transistor on its own.
That was when they used the planar transistor. That’s like a crossbar happening where the electrons could flow when one of the bars is turned on and off. But if you shrink and shrink and shrink and shrink such features on a chip, you get a problem which is comparable to single to noise.
It’s like in the audio world. If you have too much noise, you can’t make up if it’s a one or a zero. because there’s not enough electrons flowing through or they’re escaping or they’re leaking out on another way because there’s no longer a big enough or defined enough path. In order to combat that problem, they have developed what they call FinFET transistors.
So the path of the transistor where the electrons flow through, they have replaced that with a couple of fins which are standing in parallel next to each other going through the flow gate. That way you have more… surface where the electrons can flow through, which eliminates that process. But when they use the planar transistors, they could say, okay, my chip is X amount of nanometers big.
But then they used the FinFETs, which were a completely different design and also were a bit different in size and footprint. And that’s where, as they say, the marketing nanometers came into play. And everybody who had a fabrication facility could say, we have X amount of nanometers.
That’s good to point out that the current AMD chips are made at 7 nanometers and Intel were struggling with their 10 nanometers. Actually, in C, those two processes are producing pretty much the same size of transistor and are not that much different as they seem out just from the numbers point of view. So the 7 nanometers is pretty much the same as the 10 nanometer chips.
They’re just differently designed. They vary in their geometric 3D form from each other and the way they produce it with different steps. But just pure marketing term.
So don’t let marketing fool you that 7 nanometer chips are better than 10 nanometer chips. They’re pretty much the same. It’s just more of a PR rating as they call it.